The Tachyon II will be a new FPGA supporting low-latency networks of embedded devices while adhering to the VNX form factor.
Limitations on size, memory, storage, and fault tolerance leave little room for performance in embedded systems. This is especially true in the aerospace industry. We worked with the company Praesum Communications to create a new device (the Tachyon II) which can support embedded networks of devices with aerospace applications in mind. The device is designed to conform to the strict standards of devices in the aerospace sector (VNX form factor) and to allow for low-latency connections between many devices.
The Tachyon II will be an FPGA which is a chip with configurable digital logic. The FPGA ‘fabric’ can be programmed on the fly to implement desired hardware features. One of our goals was to program an implementation of the RapidIO standard into the fabric of a new FPGA. RapidIO is a technology that can drive efficient embedded networks. We used an implementation of this standard from Praesum Communications.
Another important feature of this device is that it will be powered by a RISC-V processor. RISC-V is an instruction set architecture (ISA) which is comparable to the ARM architecture found on many low-power devices. RISC-V is an open-standard as opposed to the proprietary offerings of other companies. Importantly, RISC-V can implement the minimal set of instructions necessary for a given application. As a result, RISC-V can be a lean, efficient platform for our new device.
Our team was responsible for the bring-up of any software necessary for the device, while a hardware team worked on creating a schematic. We used the Polar Fire Icicle Kit (an FPGA development platform) as the basis of our work. On the Icicle Kit, we configured and compiled a Linux kernel for RISC-V with RapidIO support enabled. Then we built the RapidIO kernel modules out-of-tree and ensured they could be properly loaded into the previously built kernel. Finally, we took an old program for pulling info on RapidIO devices on ARM architectures and modified it for use on the RISC-V Icicle Kit. Using this demo we were able to pull RapidIO device data, verifying that the RapidIO subsystem had been brought up properly.
With the software in place, all that is left is for the schematic created by the hardware team to be manufactured.
